Covered - Verilog Code Coverage Analyzer

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Covered is a Verilog code coverage utility that reads in a Verilog design and generated VCD/LXT dumpfile (or runnable in VPI module form) from that design and generates a coverage file that can be merged with other coverage files and/or used to create a coverage report. Covered also contains the coverage report utility that reads in a coverage file to produce human-readable coverage reports viewable in ASCII or GUI form. Areas of coverage measured by Covered are: line, toggle, memory, combinational logic, FSM state and FSM state transition, and assertion coverage.


• Covered User Manual